(A) Field of the Invention
The present invention relates to a method for copy propagations for a processor, and more particularly, to a method for copy propagations for a Parallel Architecture Core (PAC) processor.
(B) Description of the Related Art
In compiler theory, copy propagation attempts to replace the occurrences of targets of direct assignments with their values. Many researchers have proposed various algorithms to perform copy propagation under a variety of conditions, e.g., to perform data flow-transformation for arrays, to extend this optimization technique to parallel programs, or to generate profile information to assist this classic code optimization. However, without taking inter/intra communication costs into consideration, those propagation schemes do not properly fit into modem digital signal processor (DSP) architecture, e.g., cluster-based architecture, or irregular register files. DSPs have been found widely used in an increasing number of computationally intensive applications in fields such as mobile systems. As communications applications are moving towards conflicting requirements of higher performance and lower power consumption, DSPs have evolved into a style of large computation resources combined with restricted and/or specialized data paths and register storages. In modem DSPs, computation resources are divided into clusters with dedicated local register files to reduce hardware complexity.
Traditional copy-propagation methods applied to processors with cluster-based architectures and irregular register files tend to exhibit high frequencies of improper copy propagations.